This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-062268, filed Mar. 6, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a semiconductor integrated circuit and more particularly to a semiconductor integrated circuit having mounted thereon a pseudo SRAM (pseudo static random access memory) using a DRAM (Dynamic Random Access Memory) or FeRAM (Ferroelectric Random Access Memory) in a memory core section.
2. Description of the Related Art
A pseudo SRAM using a DRAM or FeRAM in a memory core section is commercialized in order to enhance the integration density while keeping compatibility with the existing SRAM in the application. As the conventional pseudo SRAM, a synchronous SRAM in which the internal operation is controlled according to a clock signal internally created in a time series fashion based on an external input signal, for example, a /CE (chip enable) signal is dominantly used.
Recently, the demand for pseudo SRAMs designed for mobile telephones (cellular phones) becomes stronger and it is strongly required to develop asynchronous SRAMs which can be operated asynchronously with respect to an external input signal.
Further, if a DRAM is used in the memory core section of the pseudo SRAM, a high speed operation mode such as a static column mode in which memory cells on a row selected by a row address following a /RAS (Row Address Strobe) signal are sequentially accessed by use of a column address signal is provided in many cases.
However, the conventional pseudo SRAM has a problem that the high speed operation mode of the DRAM in the memory core section cannot be attained while the pseudo SRAM is operated asynchronously with respect to the external input signal.
Therefore, it is desired to realize a semiconductor integrated circuit in which a pseudo SRAM contained therein can be operated asynchronously with respect to the external input signal and the high speed operation mode can be asynchronously executed.
Further, it is desired to realize a semiconductor integrated circuit in which the pseudo SRAM can be selectively operated in a synchronous or asynchronous fashion with respect to the external input signal.
A semiconductor integrated circuit according to a first aspect of this invention comprises a memory cell array, a first address transition detecting circuit which detects transition of a row address signal used to designate a row address of the memory cell array and transition of a column address signal used to designate a column address thereof, a second address transition detecting circuit which detects only the transition of the column address signal, a control circuit which generates an internal circuit control signal with a desired period of time required for row access to the memory cell array based on only a first detection signal generated from the first address transition detecting circuit to control the row access to the memory cell array based on the internal circuit control signal and generates a column-related circuit control signal with a desired period of time required for column access to the memory cell array based on only a second detection signal generated from the second address transition detecting circuit to control the column access to the memory cell array based on the column-related circuit control signal, and a mode discriminator which determines one of the row access and the column access to be made and performs the access control operation based on the determination result.